This invention relates to an apparatus for testing semiconductor devices and, more particularly, to such an apparatus which tests semiconductor devices by generating test vectors for application to input terminals of a device and examining the output response.
As semiconductor devices have become more and more complex, it has become increasingly difficult, yet increasingly important, to test the devices to ensure that they operate properly. In a typical semiconductor array tester, a test vector is applied to input terminals and the array output is monitored to see if the output is in agreement with the output that would be expected from a properly operating array. As a practical matter, in order to adequately test the full range of operations in an array, it is necessary to apply a long sequence of test vectors to the array and to monitor a correspondingly long sequence of outputs. If all outputs are in agreement with the expected outputs, the semiconductor array is operating properly. If one or more of the actual outputs differ from the expected values, the array outputs can be analyzed to determine the cause of the error. If the error cannot be corrected, the analysis of the failure data will be helpful in re-assessing manufacturing techniques in an attempt to reduce the number of failures.
Typical examples of testing arrangements are disclosed in the following references: U.S. Pat. No. 4,242,751 issued to Henckels et al; U.S. Pat. No. 4,108,358 issued to Niemaszyk et al; U.S. Pat. No. 3,614,608 issued to Giedd et al; U.S. Pat. No. 3,869,603 issued to Auspurg et al; U.S. Pat. No. 4,100,403 issued to Eggenberger et al; U.S. Pat. No. 4,335,457 issued to Early; U.S. Pat. No. 4,339,801 issued to Hosaka et al; U.S. Pat. No. 4,342,084 issued to Sager et al; U.S. Pat. No. 3,655,959 issued to Chernow et al.; and IBM Technical Disclosure Bulletin Vol. 19, No. 9, February, 1977, pages 3487-3488.
A typical testing arrangement may have a configuration such as shown in FIG. 1, wherein a memory 10 stores a complete vector sequence including address, data and control bits. Address generating circuitry, e.g. an address counter, in a central control computer (not shown) provides a sequence of addresses to the memory 10, and the memory 10 responds by reading out a sequence of words. Each word includes address, data and control fields, with the address field being provided to multiplexer 12, the data field being provided to multiplexer 14 and the control field being provided to the multiplexer 16. The memory chip under test, or Device Under Test (DUT), 18 includes a plurality of pins 20, and a pin electronics interface 22 includes one driver/receiver per pin. The multiplexer 12 will multiplex the address field, as appropriate, over all of the pins 20 via respective driver/receiver elements, and the multiplexers 14 and 16 will do likewise with the data and control fields.
The use of multiplexers 12, 14 and 16 allows the testing apparatus to adapt to various different pin configurations, thereby allowing the testing apparatus to be used in conjunction with a variety of different semiconductor chips. Other techniques for selectively connecting the test pattern bits to any of the DUT pins to enhance the versatility of the testing configuration are disclosed in the following references: U.S. Pat. No. 3,854,125 to Ehling et al; U.S. Pat. No. 4,216,539 to Raymond et al; U.S. Pat. No. 4,180,203 to Masters; U.S. Pat. No. 4,097,797 to Finet; U.S. Pat. No. 4,125,763 to Drabing et al; U.S. Pat. No. 4,070,565 to Borrelli; and U.S. Pat. No. 4,168,796 to Fulks et al.
A number of testing apparatus have been proposed in which the size of the pattern memory is reduced by generating at least a portion of the test pattern by some means other than the main test pattern memory. Examples of such testing systems are disclosed in the following references: U.S. Pat. No. 4,195,770 to Benton et al; U.S. Pat. No. 3,751,649 to Hart, Jr.; U.S. Pat. No. 4,313,200 to Nishiura; and IBM Technical Disclosure Bulletin Vol. 20, No. 2, July, 1977, pages 535-536.
Other miscellaneous testing arrangements are disclosed in U.S. Pat. No. 4,353,268 to Michel et al; U.S. Pat. No. 4,200,225 to Uneo et al; and U.S. Pat. No. 4,293,950 to Shimizu et al.
Despite the various improvements in the art, existing testing apparatus still suffer from a number of problems. As described by Wayne E. Sohl in "Selecting Test Patterns for 4K RAMS", IEEE Transactions on Manufacturing Technology, Vol. MFT-6, No. 3, September, 1977, pages 51-60, most test vector sequences require on the order of N.sup.2 test vectors in order to properly test an array, where N is the memory size. In testing small memory arrays, the N.sup.2 requirement is not a significant problem. However, in order to test a 64K memory array, the tester must provide in excess of 4.times.10.sup.9 test vectors. This results in the requirement of an excessively large test pattern memory. A further problem is that, since a new test pattern memory vector must be read out for each test pattern step, the tester is inherently slow, e.g., 100 mHz maximum. This results in excessively long testing time requirements. Finally, the multiplexing enables the testing apparatus to accommodate various memory part numbers having different address, data or control pins, but the multiplexing is very slow, complex and expensive. Accordingly, it is necessary to limit the flexibility of the testing apparatus by dedicating certain pins for address, data or control bits.
The above problems in test pattern memory requirements and testing apparatus operating speed become even more significant as the size of semiconductor memory arrays increases. The requirements of existing testing devices will be intolerable when testing future generation semiconductor memories, e.g., 256K RAMS.